1. Field of the Invention
This invention relates to high speed sampling circuits. More particularly, the invention relates to a circuit and method for reducing sampling distortion.
2. Background Art
A sample and hold circuit periodically captures the amplitude of a variable analog signal. In many sample and hold circuits, distortion is produced by circuit components that limit the useful voltage range of an input signal or limit the useful frequency of the input signal. Distortion may be produced, for example, by nonlinear resistance characteristics of switches in the sample and hold circuits that are caused by effects such as field effect transistor (FET) threshold turnoff, bulk effect, or manufacturing variations. Distortion may also be produced by parasitic capacitances of switches in the sample and hold circuit, nonlinear load currents in the input source resistance that are caused by semiconductor junctions of switches in the sample and hold circuits, and terminal resistance of switches in the sample and hold circuits.
These distortions are generally nonlinear functions of the applied input voltage. In a sampling circuit, the applied input voltage is the signal to be sampled. This type of sampling is called signal dependent sampling. In applications requiring low distortion and high sample fidelity, signal dependent sampling is undesirable.
Various methods are used to eliminate the distortion caused by signal dependent sampling. These methods include active cancellation circuitry, multiple sample circuits, and other distortion cancellation methods requiring additional complex and expensive circuit components. In one method, an auxiliary sampling circuit is added to produce canceling distortion that is proportionally larger with respect to the sampled signal than the distortion produced in the main sampling circuit.
A simple and inexpensive method of eliminating signal dependent sampling distortion is to isolate the sample hold device from the distortion causing events. This method locks the sample value in the hold device before opening the sampling switch and initiating the distortion causing event. This method is simple to implement and requires only minor hardware changes. However, there are limitations in the sample and hold control circuitry that prohibit its use at high sampling rates.
What is needed is a circuit and method for eliminating distortion, caused by signal dependant sampling, that does not require complex or expensive circuitry and is suitable for use in high speed sampling applications.
The invention comprises a circuit and method for aligning pulse edges used to control a sample and hold circuit. The multi-phase alignment circuit comprises an edge discriminator connected to a first summer, a second summer, and a rate adjuster. The second summer is also connected to the rate adjuster. The edge discriminator receives a clock signal and separates the clock signal into rising and falling edges. The rate adjuster adjusts the slope of one of the falling edges to a desired value. The rising edges and the falling edges are summed in the first summer and output as a clock signal. The rising edges and the adjusted falling edges are summed in the second summer and output as an adjusted clock signal. The rising edges of the clock signal and the adjusted clock signal are aligned. The clock signal and adjusted clock signal control a high speed sample and hold circuit.